You are given the following C code, which is executed on a RISC$-$V processors with a $5-$stage pipeline, including support for forwarding and hazard detection.

for $($i$=0$; i$<4$; i$++)\{$

for $($j$=0$;j$<8$; j$++)\{$

a$[$i$][$j$]=$ b$[$j$][$i$]$;

$...//$ bne instruction at the end of loop body

$\}$

$\}$

The following questions concern the branch instruction at the end of the innermost loop's body. If the pipeline resolves branches in the decode $($ID$)$ stage, meaning it does the branch target address calculation and the branch comparison in the ID stage, how many stall cycles will this code have because of the innermost loop's branch instruction? If the pipeline:

has a two$-$bit branch predictor, as shown in the figure below, and,

both the branch outcome and the target of the branch are predicted in the IF stage, and,

the branch predictor resolves the actual branch target address and taken$/$not taken direction in the ID stage, and,

the branch predictor does not know the target address of the branch until the branch is executed for the first time, and,

the branch predictor state is initialized to predict taken;

How many stall cycles will this code incur because of branches?