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systems analysis and design
Analysis And Design Of Energy Systems 3rd Edition B. Hodge, Robert Taylor - Solutions
15. Why are I/O buses provided with clock signals?
14. Of programmed I/O, interrupt-driven I/O, DMA, or channel I/O, which is most suitable for processing the I/O of a:a) Mouseb) Game controllerc) CDd) Thumb drive or memory stick Explain your answers.
13. A generic DMA controller consists of the following components:• Address generator• Address bus interface• Data bus interface• Bus requestor• Interrupt signal circuits• Local peripheral controller The local peripheral controller is the circuitry that the DMA uses to select among the
12. A CPU with interrupt-driven I/O is busy servicing a disk request. While the CPU is midway through the disk-service routine, another I/O interrupt occurs.a) What happens next?b) Is it a problem?c) If not, why not? If so, what can be done about it?
11. Name the four types of I/O architectures. Where are each of these typically used, and why are they used there?
10. Amdahl’s Law is as applicable to software as it is to hardware. An oft-cited programming truism states that a program spends 90% of its time executing 10% of its code. Thus, tuning a small amount of program code can often have an enormous effect on the overall performance of a software
9. How would you answer exercise 8 if the system activity consists of 55% processor time and 45%disk activity?
8. Suppose the daytime processing load consists of 60% CPU activity and 40% disk activity. Your customers are complaining that the system is slow. After doing some research, you learn that you can upgrade your disks for $8,000 to make them 2.5 times as fast as they are currently. You have also
7. Your friend has just bought a new personal computer. She tells you that her new system runs at 1GHz, which makes it more than three times faster than her old 300MHz system. What would you tell her? (Hint: Consider how Amdahl’s Law applies.)
6. Suppose that you are designing an electronic musical instrument. The prototype system occasionally produces off-key notes, causing listeners to wince and grimace. You have determined that the cause of the problem is that the system becomes overwhelmed in processing the complicated input. You are
5. Suppose that you are designing a game system that responds to players’ pressing buttons and toggling joysticks. The prototype system is failing to react in time to these input events, causing noticeable annoyance to the gamers. You have calculated that you need to improve overall system
4. Suppose your company has decided that it needs to make certain busy servers 30% faster.Processes in the workload spend 70% of their time using the CPU and 30% on I/O. In order to achieve an overall system speedup of 30%:a) How much faster does the CPU need to be?b) How much faster does the disk
3. Suppose your company has decided that it needs to make certain busy servers 50% faster.Processes in the workload spend 60% of their time using the CPU and 40% on I/O. In order to achieve an overall system speedup of 25%:a) How much faster does the CPU need to be?b) How much faster does the disk
2. Calculate the overall speedup of a system that spends 40% of its time in calculations with a processor upgrade that provides for 100% greater throughput.
1. Calculate the overall speedup of a system that spends 65% of its time on I/O with a disk upgrade that provides for 50% greater throughput.
49. What is a memristor, and how does it store data?
48. How does CNT storage work?
47. What is the general idea behind MEMS storage?
46. Explain how holographic storage works.
45. What does the superparamagnetic limit mean for disk drives?
44. What is the significance of the superparamagnetic limit?
43. What are hybrid RAID systems?
42. Which RAID level uses a mirror (shadow) set?
41. Which RAID levels offer the best economy while providing adequate redundancy?
40. Which RAID levels offer the best performance?
39. What are two popular tape formats that use serpentine recording?
38. Explain how serpentine recording differs from helical scan recording.
37. Why is magnetic tape a popular storage medium?
36. Name the three methods for recording WORM disks.
35. Explain why Blu-Ray discs hold so much more data than regular DVDs.
34. How do DVDs store so much more data than regular CDs?
33. Do CDs that store data use recording sessions?
32. Why are CDs especially useful for long-term data storage?
31. How is the format of a CD that stores music different from the format of a CD that stores data? How are the formats alike?
30. Magnetic disks store bytes by changing the polarity of a magnetic medium. How do optical disks store bytes?
29. What is the acronym for computer output that is written directly to optical media rather than paper or microfiche?
28. What is the name for robotic optical disk library devices?
27. What is wear leveling, and why is it needed for SSDs?
26. How do enterprise SSDs differ from SSDs intended for laptop computers?
25. What is short stroking, and how does it affect the relative cost per gigabyte of SSDs?
24. By how much is an SSD faster than a magnetic disk?
23. Explain the differences between an SSD and a magnetic disk.
22. What is the sum of rotational delay and seek time called?
21. What is seek time?
20. What is zoned-bit recording?
19. What are the major physical components of a rigid disk drive?
18. Explain the relationship among disk platters, tracks, sectors, and clusters.
17. Why are magnetic disks called direct access devices?
16. What is settle time, and what can be done about it?
15. What distinguishes an asynchronous bus from a synchronous bus?
14. What is multiplexing?
13. How is channel I/O similar to DMA?
12. How is channel I/O different from interrupt-driven I/O?
11. What does it mean when someone refers to I/O as bursty?
10. Why does DMA require cycle stealing?
9. What is a bus master?
8. How does direct memory access (DMA) work?
7. How are address vectors used in interrupt-driven I/O?
6. What is polling?
5. Explain how programmed I/O is different from interrupt-driven I/O.
4. Name three types of durable storage.
3. What is a protocol, and why is it important in I/O bus technology?
2. What is speedup?
1. State Amdahl’s Law in words.
30. Look up a specific vendor’s specifications for memory, and report the memory access time, cache access time, and cache hit rate (and any other data the vendor provides).
29. Name two ways that, as a programmer, you can improve cache performance.
28. Pick a specific architecture (other than the one covered in this chapter). Do research to find out how your architecture approaches the concepts introduced in this chapter, as was done for Intel’s Pentium.
27. Consider a system that has multiple processors where each processor has its own cache, but main memory is shared among all processors.a) Which cache write policy would you use?b) The Cache Coherency Problem. With regard to the system just described, what problems are caused if a processor has a
26.a) If you are a computer builder trying to make your system as price-competitive as possible, what features and organization would you select for its memory hierarchy?b) If you are a computer buyer trying to get the best performance from a system, what features would you look for in its memory
25. A system implements a paged virtual address space for each process using a one-level page table.The maximum size of virtual address space is 16MB. The page table for the running process includes the following valid entries (the → notation indicates that a virtual page maps to the given page
24. Does a TLB miss always indicate that a page is missing from memory? Explain.
23. Given a virtual memory system with a TLB, a cache, and a page table, assume the following:• A TLB hit requires 5ns.• A cache hit requires 12ns.• A memory reference requires 25ns.• A disk reference requires 200ms (this includes updating the page table, cache, and TLB).• The TLB hit
22. You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided into blocks, where each block is represented by a
21. Suppose we have 210 bytes of virtual memory and 28 bytes of physical main memory. Suppose the page size is 24 bytes.a) How many pages are there in virtual memory?b) How many page frames are there in main memory?c) How many entries are in the page table for a process that uses all of virtual
20. Suppose you have a byte-addressable virtual address memory system with eight virtual pages of 64 bytes each, and four page frames. Assuming the following page table, answer the questions below:a) How many bits are in a virtual address?b) How many bits are in a physical address?c) What physical
19. Suppose a process page table contains the entries shown below. Using the format shown in Figure 6.22a, indicate where the process pages are located in memory.Frame Valid Bit- 0 3 1- 0- 0 2 1 0 1- 0 1 1
18. Suppose a process page table contains the entries shown below. Using the format shown in Figure 6.17a, indicate where the process pages are located in memory. Frame Valid Bit 1 1- 0 0 1 3 1- 0- 0 2 1- 0
17. Redo exercise 16, assuming now that cache is 16-way set associative. Address TAG Cache Location (set) Offset within Block OXOFFOFABA 0x00000011 OXOFFFFFFE 0x23456719 OXCAFEBABE
16. Assume a direct mapped cache that holds 4096 bytes, in which each block is 16 bytes. Assuming that an address is 32 bits and that cache is initially empty, complete the table that follows. (You should use hexadecimal numbers for all answers.) Which, if any, of the addresses will cause a
15. Suppose a byte-addressable computer using 4-way set associative cache has 216 words of main memory (where each word is 32 bits) and a cache of 32 blocks, where each block is 4 words.Show the main memory address format for this machine. (Hint: Because this architecture is byte addressable, and
14. Consider a byte-addressable computer with 24-bit addresses, a cache capable of storing a total of 64KB of data, and blocks of 32 bytes. Show the format of a 24-bit memory address for:a) direct mappedb) associativec) 4-way set associative
13. A direct mapped cache consists of 8 blocks. Byte-addressable main memory contains 4K blocks of 8 bytes each. Access time for the cache is 22ns, and the time required to fill a cache slot from main memory is 300ns. (This time allows us to determine that the block is missing and bring it into
12. Given a byte-addressable memory with 256 bytes, suppose a memory dump yields the results shown below. The address of each memory cell is determined by its row and column. For example, memory address 0x97 is in the 9th row, 7th column, and contains the hexadecimal value 43. Memory location 0xA3
11. Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16-byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program.Suppose this computer uses direct-mapped cache. The format of a
10. Suppose a byte-addressable computer using set associative cache has 221 bytes of main memory and a cache of 64 blocks, where each cache block contains 4 bytes.a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of
9. Suppose a byte-addressable computer using set associative cache has 216 bytes of main memory and a cache of 32 blocks, and each cache block contains 8 bytes.a) If this cache is 2-way set associative, what is the format of a memory address as seen by the cache; that is, what are the sizes of the
8. A 2-way set associative cache consists of 4 sets. Main memory contains 2K blocks of 8 bytes each and byte addressing is used.a) Show the main memory address format that allows us to map addresses from main memory to cache. Be sure to include the fields as well as their sizes.b) Compute the hit
7. Assume that a system’s memory has 128M bytes. Blocks are 64 bytes in length, and the cache consists of 32K blocks. Show the format for a main memory address assuming a 2-way set associative cache mapping scheme and byte addressing. Be sure to include the fields as well as their sizes.
6. Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each block contains 64 bytes.a) How many blocks of main memory are there?b) What is the format of a memory address as seen by cache; that is, what are the sizes of the
5. Suppose a computer using fully associative cache has 224 bytes of byte-addressable main memory and a cache of 128 blocks, where each cache block contains 64 bytes.a) How many blocks of main memory are there?b) What is the format of a memory address as seen by the cache; that is, what are the
4. Suppose a computer using fully associative cache has 216 bytes of byte-addressable main memory and a cache of 64 blocks, where each cache block contains 32 bytes.a) How many blocks of main memory are there?b) What is the format of a memory address as seen by the cache; that is, what are the
3. Suppose a computer using direct mapped cache has 232 bytes of byte-addressable main memory and a cache size of 512 bytes, and each cache block contains 64 bytes.a) How many blocks of main memory are there?b) What is the format of a memory address as seen by cache; that is, what are the sizes of
2. Suppose a computer using direct mapped cache has 232 bytes of byte-addressable main memory and a cache of 1024 blocks, where each cache block contains 32 bytes.a) How many blocks of main memory are there?b) What is the format of a memory address as seen by the cache; that is, what are the sizes
1. Suppose a computer using direct mapped cache has 220 bytes of byte-addressable main memory and a cache of 32 blocks, where each cache block contains 16 bytes.a) How many blocks of main memory are there?b) What is the format of a memory address as seen by the cache; that is, what are the sizes of
39. What causes external fragmentation, and how can it be fixed?
38. When would a system ever need to page its page table?
37. What are the advantages and disadvantages of virtual memory?
36. What is a TLB, and how does it improve EAT?
35. What are the components (fields) of a virtual address?
34. What causes internal fragmentation?
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