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systems analysis and design
Analysis And Design Of Energy Systems 3rd Edition B. Hodge, Robert Taylor - Solutions
33. What is a page fault?
32. Discuss the pros and cons of paging.
31. What is the objective of paging?
30. What is the difference between a virtual memory address and a physical memory address? Which is larger? Why?
29. What is the advantage to a nonblocking cache?
28. Explain the differences between inclusive and exclusive cache.
27. Explain the differences among L1, L2, and L3 cache.
26. Why would a system contain a victim cache? A trace cache?
25. What are the advantages of a Harvard cache?
24. Explain the difference between a unified cache and a Harvard cache.
23. Describe the advantages and disadvantages of the two cache write policies.
22. What is a dirty block?
21. When does caching behave badly?
20. Explain how to derive an effective access time formula.
19. What, exactly, is effective access time (EAT)?
18. What is the worst-case cache behavior that can develop using LRU and FIFO cache replacement policies?
17. Why is the optimal cache replacement policy important?
16. Explain the four cache replacement policies presented in this chapter.
15. What are the three fields in a set associative cache address, and how are they used to access a location in cache?
14. Direct mapped cache is a special case of set associative cache where the set size is 1. So fully associative cache is a special case of set associative cache where the set size is ___.
13. Explain how set associative cache combines the ideas of direct and fully associa tive cache.
12. Explain how fully associative cache is different from direct mapped cache.
11. How does associative memory differ from regular memory? Which is more expensive and why?
10. What are the three fields in a direct mapped cache address? How are they used to access a word located in cache?
9. Cache is accessed by its ________, whereas main memory is accessed by its _______.
8. Which of L1 or L2 cache is faster? Which is smaller? Why is it smaller?
7. Give two noncomputer examples of the concept of cache.
6. What are the three forms of locality?
5. Explain the concept of locality of reference, and state its importance to memory systems.
4. Explain the concept of a memory hierarchy. Why did your authors choose to represent it as a pyramid?
3. Name three different applications where ROMs are often used.
2. What are the advantages of using DRAM for main memory?
1. Which is faster, SRAM or DRAM?
12. Data dependencies occur in a pipeline when multiple instructions need the CPU.
11. Resource conflicts occur in a pipeline when there are multiple instructions that require the same resource.
10. The effective address of an operand is the value of its actual address in memory.
9. Instruction set orthogonality refers to the characteristic in an instruction set architecture where each instruction has a “backup” instruction that performs the same operation.
8. Expanding opcodes make instruction decoding much easier than when it is not used.
7. Fixed-length instruction format typically results in better performance than variable-length instruction format.
6. Most architectures today are accumulator based.
5. Stack architectures have good code density and a simple model for evaluation of expressions, but do not allow random access, which can cause a problem with the generation of efficient code.
4. The term “endian” refers to an architecture’s byte ordering.
3. An instruction takes less time to execute on a processor using an instruction pipeline than on a processor without an instruction pipeline.
2. The advantage of zero-address instruction computers is that they have short programs; the disadvantage is that the instructions require many bits, making them very long.
1. Most computers typically fall into one of three types of CPU organization: (1) general register organization; (2) single accumulator organization; or (3) stack organization.
30. Pick an architecture (other than those covered in this chapter). Do research to find out how your architecture approaches the concepts introduced in this chapter, as was done for Intel, MIPS, and Java.
29. Suppose an instruction takes four cycles to execute in a nonpipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a four-stage pipeline, that instruction still takes four
28. The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: an opcode field; a mode field to specify one of seven addressing modes; a register address field to specify one of 60 registers; and a memory address field. Assume an
27. A digital computer has a memory unit with 24 bits per word. The instruction set consists of 150 different operations. All instructions have an operation code part (opcode) and an address part(allowing for only one address). Each instruction is stored in one word of memory.a) How many bits are
26. Write code to implement the expression A = (B + C) × (D + E) on three-, two-, one-, and zeroaddress machines. In accordance with programming language practice, computing the expression should not change the values of its operands.
25. Assuming the same stages as in Example 5.12, explain the potential pipeline hazards (if any) in each of the following code segments.a) X = R2 + Y R4 = R2 + Xb) R1 = R2 + X X = R3 + Y Z = R1 + X
24. A nonpipelined system takes 100ns to process a task. The same task can be processed in a fivestage pipeline with a clock cycle of 20ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the theoretical speedup that could be achieved with the pipeline system over a nonpipelined
23. A nonpipelined system takes 200ns to process a task. The same task can be processed in a fivesegment pipeline with a clock cycle of 40ns. Determine the speedup ratio of the pipeline for 200 tasks. What is the maximum speedup that could be achieved with the pipeline unit over the nonpipelined
22. Suppose we have the instruction Load 500. Given that memory and register R1 contain the values below:and assuming that R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator and fill in the table below: Mode Value Loaded into AC Immediate Direct
21. Suppose we have the instruction Load 1000. Given that memory and register R1 contain the values below:and assuming that R1 is implied in the indexed addressing mode, determine the actual value loaded into the accumulator and fill in the table below: Mode Value Loaded into AC Immediate Direct
20. What is the difference between using direct and indirect addressing? Give an example.
19. Given 16-bit instructions, is it possible to use expanding opcodes to allow the following to be encoded assuming we have a total of 32 registers? If so, show the encoding. If not, explain why is it not possible.• 60 instructions with two register operands• 30 instructions with one register
18. Suppose a computer has an instruction format with space for an opcode and either three register values or one register value and an address. What are the various instruction formats that could be used for an ADD instruction on this machine?
17.a) In a computer instruction format, the instruction length is 11 bits and the size of an address field is 4 bits. Is it possible to have 5 two-address instructions 45 one-address instructions 32 zero-address instructions using the specified format? Justify your answer.b) Assume that a computer
16.a) Write the following expression in postfix (reverse Polish) notation. Remember the rules of precedence for arithmetic operators!b) Write a program to evaluate the above arithmetic statement using a stack-organized computer with zero-address instructions (so only Pop and Push can access
15. Explain how a stack is used to evaluate the RPN expressions from exercise 13.
14. Convert the following expressions from reverse Polish notation to infix notation.a) W X Y Z – + ×b) U V W X Y Z + × + × +c) X Y Z + V W – × Z + +
13. Convert the following expressions from reverse Polish notation to infix notation.a) 12 8 3 1 + – /b) 5 2 + 2 × 1 + 2 ×c) 3 5 7 + 2 1 – × 1 + +
12. Convert the following expressions from infix to reverse Polish (postfix) notation.a) X × Y + W × Z + V × Ub) W × X + W × (U × V + Z)c) (W × (X + Y × (U × V)))/(U × (X + Y))
11. Convert the following expressions from infix to reverse Polish (postfix) notation.a) (8 – 6)/2b) (2 + 3) × 8/10c) (5 × (4 + 3) × 2 – 6)
10. A computer has 32-bit instructions and 12-bit addresses. Suppose there are 250 two-address instructions. How many one-address instructions can be formulated? Explain your answer.
9. There are reasons for machine designers to want all instructions to be the same length. Why is this not a good idea on a stack machine?
8. The Population Studies Institute monitors the population of the United States. In 2008, this institute wrote a program to create files of the numbers representing populations of the various states, as well as the total population of the United States. This program, which runs on a Motorola
7. What kinds of problems do you think endian-ness can cause if you wished to transfer data from a big endian machine to a little endian machine? Explain.
6. The first two bytes of a 2M × 16 main memory have the following hex values:• Byte 0 is FE• Byte 1 is 01 If these bytes hold a 16-bit two’s complement integer, what is its actual decimal value if:a) memory is big endian?b) memory is little endian?
5. Consider a 32-bit hexadecimal number stored in memory as follows:Address Value 100 2A 101 102 103 C2 08 1Ba) If the machine is big endian and uses two’s complement representation for integers, write the 32-bit integer number stored at address 100 (you may write the number in hex).b) If the
4. Assume a computer that has 32-bit integers. Show how each of the following values would be stored sequentially in memory, starting at address 0x100, assuming that each address holds 1 byte. Be sure to extend each value to the appropriate number of bits. You will need to add more rows(addresses)
3. Fill in the following table to show how the given integers are represented, assuming that 16 bits are used to store values and the machine uses two’s complement notation. Integer Binary Hex 28 2216 -18675 -12 31456 4 Byte Big Endian (Hex value as seen in memory) 4 Byte Little Endian (Hex value
2. Show how the following values would be stored by byte-addressable machines with 32-bit words, using little endian and then big endian format. Assume that each value starts at address 1016. Draw a diagram of memory for each, placing the appropriate values in the correct (and labeled) memory
1. Assume you have a byte-addressable machine that uses 32-bit integers and you are storing the hex value 1234 at address 0:a) Show how this is stored on a big endian machine.b) Show how this is stored on a little endian machine.c) If you wanted to increase the hex value to 123456, which byte
25. Give an example of a current stack-based architecture and a current GPR-based architecture. How do they differ?
24. Explain Java bytecodes.
23. List several ways in which the Intel and MIPS ISAs differ. Name several ways in which they are the same.
22. Explain superscalar, superpipelining, and VLIW architectures.
21. What are the two types of ILP, and how do they differ?
20. What are the pipeline conflicts that can cause a slowdown in the pipeline?
19. What is the theoretical speedup for a 4-stage pipeline with a 20ns clock cycle if it is processing 100 tasks?
18. Explain the concept behind instruction pipelining.
17. Why do we need so many different addressing modes?
16. How does indexed addressing differ from based addressing?
15. Give examples of immediate, direct, register, indirect, register indirect, and indexed addressing.
14. What is an address mode?
13. Explain what it means for an instruction set to be orthogonal.
12. What is the difference between an arithmetic shift and a logical shift?
11. Name the seven types of data instructions and explain each.
10. Why might stack architectures represent arithmetic expressions in reverse Polish notation?
9. Which is likely to be longer (have more instructions): a program written for a zero-address architecture, a program written for a one-address architecture, or a program written for a two-address architecture? Why?
8. How does an architecture based on zero operands ever get any data values from memory?
7. What are the pros and cons of fixed-length and variable-length instructions? Which is currently more popular?
6. How do memory-memory, register-memory, and load-store architectures differ? How are they the same?
5. We can design stack architectures, accumulator architectures, or general-purpose register architectures. Explain the differences between these choices and give some situations where one might be better than another.
4. If a byte-addressable machine with 32-bit words stores the hex value 98765432, indicate how this value would be stored on a little endian machine and on a big endian machine. Why does “endianness”matter?
3. What is an expanding opcode?
2. Several design decisions exist with regard to instruction sets. Name four and explain.
1. Explain the difference between register-to-register, register-to-memory, and memory-to-memory instructions.
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