If there is forwarding, for the first five cycles during the execution of this code, specify which signals are asserted in each cycle by hazard detection and forwarding units in Figure 4.60.

This exercise is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequences of instructions, and assume that it is executed on a 5-stage pipelined datapath:

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PCWrite PC Instruction memory IF/DWrite IF/ID Instruction Hazard detection unit Control Registers MUX IF/ID. RegisterRs IF/ID. RegisterRt IF/ID. RegisterRt IF/ID. RegisterRd ID/EX.RegisterRt ID/EX.MemRead ID/EX WB M EX Rt Rd. Rs Rt MUX MUX MUX EX/MEM WB ALU Forwarding unit M Data memory MEM/WB WB MUX