If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?

In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:

a. b. IF 250ps 200ps ID 350ps 170ps EX 150ps 220ps MEM 300ps 210ps WB 200ps 150ps