If we want to add this instruction to the MIPS ISA, discuss the changes to the pipeline (which stages, which structures in which stage) that are needed to directly (without micro-ops) support this instruction.

This exercise is intended to help you better understand the last pitfall from failure to consider pipelining in instruction set design. The first four problems in this exercise refer to the following new MIPS instruction:

a. Instruction SWINC Rt, Offset (Rs) b. SWI Rt, Rd (Rs) Interpretation Mem[Reg[Rs]+Offset]=Reg [Rt] Reg[Rs ] Reg[Rs]+4 Mem[Reg[Rd]+Reg [Rs ]]= Reg[Rt]