How often do you expect this instruction can be used? Do you think that we would be justified if we added this instruction to the MIPS ISA?

This exercise is intended to help you better understand the last pitfall from failure to consider pipelining in instruction set design. The first four problems in this exercise refer to the following new MIPS instruction:

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a. Instruction SWINC Rt, Offset (Rs) b. SWI Rt, Rd (Rs) Interpretation Mem[Reg[Rs]+Offset]=Reg [Rt] Reg[Rs ] Reg[Rs]+4 Mem[Reg[Rd]+Reg [Rs ]]= Reg[Rt]