Write a test bench to test the counter of Problem 2.48. The test bench should generate a

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Write a test bench to test the counter of Problem 2.48. The test bench should generate a clock with a 100-ns period. The counter should be loaded on the first clock, then it should count for 5 clocks, then it should do nothing for 2 clocks, then it should continue counting for 10 clocks. The test bench port should output the current time (in time units, not the count) whenever S5 = 1. Use only concurrent statements in your test bench.

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Digital Systems Design Using Verilog

ISBN: 978-1285051079

1st edition

Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

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