Complete the following Verilog code to implement a counter that counts in the following sequence: Q = 1000, 0111, 0110, 0101, 0100, 0011, 1000, 0111, 0110, 0101, 0100, 0011, … (repeats). The counter is synchronously loaded with 1000 when Ld8 = 1. It goes through the prescribed sequence when Enable = 1. The counter outputs S₅ = 1 whenever it is in state 0101. Do not change the provided structure of the following module in any way. Your code must be synthesizable.
module countQ1(clk,Ld8,Enable,S5,Q);
input clk,Ld8,Enable;
output reg S5;
output reg[3:0] Q;
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endmodule