$10.($a$)$ A four$-$stage pipeline is shown below. Delays for the stages S$1,$ S$2,$ S$3$ and S$4$ are $5$

ns$,6$ ns$,11$ ns and $8$ ns respectively. Delay for the latches is $1$ ns each. Calculate the speed up

achieved by the pipelined architecture under ideal conditions as compared to the

corresponding non$-$pipeline implementation.