$1.(12$ pts$)$ Assume that logic blocks needed to implement a processor$$s datapath have the following latencies:

I$-$Mem Add Mux ALU Regs D$-$Mem Sign$-$Extend Shift$-$Left$-2$

I$-$Mem Add Mux ALU Regs D$-$Mem Imm$-$Gen Shift$-$Left$-1$

$250$ps $150$ps $25$ps $200$ps $150$ps $250$ps $50$ps $30$ps

a$.(2$ pts$)$ What is the latency of a R$-$type instruction $($i$.$e$.,$ how long must the clock period be to ensure that this instruction works correctly$)?$

b$.(2$ pts$)$ What is the latency of ld$?$

c$.(2$ pts$)$ What is the latency of beq?

d$.(2$ pts$)$ What is its latency of the following I$-$type instruction?

addi x$10,$ x$11,128$

What is its latency?

e$.(4$ pts$)$ Describe the execution flow of a sd instruction. What is its latency?