1. For the circuit below, the propagation delay through the ALU is 250ps, the contamination delay through the ALU is 5ps, the propagation delay through the shifter is 150ps, the contamination delay through the shifter is 4ps, the propagation delay through the Hamming code circuit is 110ps, the contamination delay through Hamming code circuit is 3ps, the MSFF clock-to-q propagation delay is 60ps, the Master Slave Flip-Flop (MSFF) clock-to-q contamination delay is 14ps, the MSFF setup time is 40ps, and the MSFF hold time is 10ps. What is the minimum clock cycle time? Is the hold time constraint met for all of the registers ? Show your equations and calculations. A 64 R S 64 64 64 Shifter 64 71 ALU 71 Hamming Code Generator and Checker 64 B Registers are made MSFF in parallel 7 Check bits