Question: 1 module my_counter (clk, reset, out); 2. input clk, reset; 3 output (2:0] out; 4 reg (2:0] temp = 3'b111; 5 6 always @(negedge clk,

1 module my_counter (clk, reset, out); 2. input clk, reset; 3

1 module my_counter (clk, reset, out); 2. input clk, reset; 3 output (2:0] out; 4 reg (2:0] temp = 3'b111; 5 6 always @(negedge clk, posedge reset) 7 begin 8 if (reset) 9 temp

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