Question: 1. Write structural Verilog code for 3 to 8 decoder shown below 2. Write test bench file for the 3 to 8 decoder and generate

1. Write structural Verilog code for 3 to 8 decoder shown

1. Write structural Verilog code for 3 to 8 decoder shown below 2. Write test bench file for the 3 to 8 decoder and generate test bench waveform 3. Generate schematic view for this decoder Oy C 0; 2 to 4 Decoder B Oy 0 . Os Oy 2 to 4 Decoder Os 04

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