1: Write the Verilog code and testbench for a 16-bit Serial adder using Moore FSM design technique..

2: Following is the code of a 4-bit parallel register. What are the errors?

module Reg4(I, Q, Clk, Rst);

input [3:0] I;

output [3:0] Q;

wire [3:0] Q;

input Clk, Rst;

always @(Clk) begin

if (Rst == 1 )

Q <= 4'b0000;

else

Q <= I;

end

endmodule NOTE: KINDLY ANSWER BOTH PARTS PLEASE.