4) Consider the following RISC-V mnemonic machine language program 400200 LD 400204 LD 400208 LD 40020C LD 400210 ADDI 400214 ADD 400218 BNE 40021C ADDI 400220 JALR 400224 SD X5, 0(X12) X6, 8(X12) X7, 0(X5) X28, 8(X5) X6, X6, (-D1o X29, X28, X7 X6, XO, (-10)1oIGo to location 400208 X5, X5, 10 XO, 0(X1) X29, 10(X12) // X12 initially has 10000000 // Return from function 10000008 2 10000010? The RISC-V CPU is pipelined as explained in class : It has forwardings, delayed branches and write-in-the-first-half, read-in-the-second-half register usage. Assume also that there is a perfect memory, with no stalls The above code is written for the pipelined RISC-V CPU since independent instructions are placed after the LD and BNE instructions. Show the execution of the code for which you show all the necessary forwarding, register-read ing-writing and resolved data hazard types as done in class 4) Consider the following RISC-V mnemonic machine language program 400200 LD 400204 LD 400208 LD 40020C LD 400210 ADDI 400214 ADD 400218 BNE 40021C ADDI 400220 JALR 400224 SD X5, 0(X12) X6, 8(X12) X7, 0(X5) X28, 8(X5) X6, X6, (-D1o X29, X28, X7 X6, XO, (-10)1oIGo to location 400208 X5, X5, 10 XO, 0(X1) X29, 10(X12) // X12 initially has 10000000 // Return from function 10000008 2 10000010? The RISC-V CPU is pipelined as explained in class : It has forwardings, delayed branches and write-in-the-first-half, read-in-the-second-half register usage. Assume also that there is a perfect memory, with no stalls The above code is written for the pipelined RISC-V CPU since independent instructions are placed after the LD and BNE instructions. Show the execution of the code for which you show all the necessary forwarding, register-read ing-writing and resolved data hazard types as done in class