Question: 4. For a direct-mapped design with a 64-bit address, the following bits of the address are used to access the cache. Tag Index 9-5 offset

4. For a direct-mapped design with a 64-bit address, the following

4. For a direct-mapped design with a 64-bit address, the following bits of the address are used to access the cache. Tag Index 9-5 offset 4-0 63-10 a. What the cache line size (in words)? b. How many entries does the cache have? c. What is the ratio between total bits required for such a cache implementation over the data storage bits

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