$5-$ Calculate this code sequence's baseline performance $($in cycles, per loop iteration$),$ assuming that no new instruction's execution can begin until the previous instruction's execution completes. Each instruction requires one clock cycle to execute.

Consider:

$-$ A branch shadow cycle is required.

$-$ Any additional latency due to instruction dependencies.

Loop:

LD F$11,0($Rw$)$

ADDD F$11,$ F$3,$ F$11$

ADDD F$13,$ F$5,$ F$7$

LD F$1,0($Rz$)$

DIVD F$5,$ F$1,$ F$3$

MULTD F$7,$ F$5,$ F$9$

ADDI Rz$,$ F$1,\backslash$#$4$

ADDI Rw$,$ F$7,\backslash$#$4$

SD Rz$,0($Rx$)$

SUB R$21,$ R$6,$ Rz

BNZ R$21,$ Loop