$6.$ Consider the following verilog modules.$$

Module m$1($a$,$b$,$c$,$d$)$;$$

Input a$,$b$,$c;$$

Output d;$$

Assign d $=($a& ~ c$)|($b & c$)$;$$

End module$$

Module m$2($in$,$ s$,$ out$)$;$$

Input $[3$:$0]$ in;$$

Input $[1$:$0]$ s;

Output out;$$

m$1$ x $($in $[0],$ in $[1],$ s $[0],$ w $[0])$;$$

m$1$ y $($in $[2],$ in $[3],$ s $[0],$ w $[1])$;$$

m$1$ z $($w $[0],$ w $[1],$ s $[1],$ out$)$;

End module$$

a$)$ sketch the corresponding circuit $($when sketching m$2,$ keep m$1$ as a module, do not expand it into gates$).$

b$)$ what standard type of module does m$2$ implement?$6.$ Consider the following verilog modules.

Module m$1($a$,$b$,$c$,$d$)$;

Input a$,$b$,$c;

Output d;

Assign $\backslash ($ d$=($a $\backslash$& $\backslash$sim c$)\backslash$mid$($b $\backslash$& c$)\backslash )$;

End module

Module m$2($in$,$ s$,$ out$)$;

Input $[3$:$0]$ in;

Input $[1$:$0]$ s;

Output out;

m$1$ x $($in $[0],$ in $[1],$ s $[0],$ w $[0])$;

m$1$ y $($in $[2],$ in $[3],$ s $[0],$ w $[1])$;

m$1$ z $($w $[0],$ w $[1],$ s $[1],$ out$)$;

End module

a$)$ sketch the corresponding circuit $($when sketching m$2,$ keep m$1$ as a module, do not expand it into gates$).$

b$)$ what standard type of module does m $2$ implement?