Consider the following verilog code:

module m$1($a$,$b$,$c$,$d$)$;

input a$,$b$,$c;

output d;

assign d $=($a & ~c$)|($b & c$)$;

endmodule

module m$2($in$,$s$,$out$)$;

input$[3$:$0]$ in;

input$[1$:$0]$ s;

output out;

wire$[1$:$0]$ w:

m$1$ x$($in$[0],$in$[1],$s$[0],$w$[0])$;

m$1$ y$($in$[2],$in$[3],$s$[0],$w$[1])$;

m$1$ z$($w$[0],$ w$[1],$ s$[1],$ out$)$;

endmodule

a$)$ sketch the corresponding circuits $($ when sketching m$2$ keep m$1$ as a module, do not expand into gates$)$

B$)$ what standard type of module does m$2$ implement?