A processor has a 32-byte memory and an 8-byte direct-mapped cache. Table 0 shows the current state of the cache. Write hit or miss under the each address in the memory reference sequence below. Show the new state of the cache for each miss in a new table, label the table with the address, and bold the change: (20 points)

Hint: This is similar to example on page 386 387 (Example 5.9) or slides 6 11 in Chapter 5 Part 2 PowerPoint slides.

Addr	10011	00001	00110	01010	01110	11001	00001	11100	10100
Hit/Miss

0. Initial State

Index	V	Tag	Data
000	N
001	Y	00	Mem(00001)
010	N
011	Y	11	Mem(11011)
100	Y	10	Mem(10100)
101	Y	01	Mem (01101)
110	Y	00	Mem(00110)
111	N

1.______________________________________

Index	V	Tag	Data
000
001
010
011
100
101
110
111

2._______________________________________

3.______________________________________

Index	V	Tag	Data
000
001
010
011
100
101
110
111

4.________________________________________

Index	V	Tag	Data
000
001
010
011
100
101
110
111

5. ________________________________________

Index	V	Tag	Data
000
001
010
011
100
101
110
111

6._________________________________________

Index	V	Tag	Data
000
001
010
011
100
101
110
111

7.________________________________________

Index	V	Tag	Data
000
001
010
011
100
101
110
111

What is the hit and miss rate of the direct-mapped cache in the exercise above? (5 points)