a. What is the cache block size(in words)?

b. How many entries does the cache have?

c. How many blocks are replaced?

d. What is the hit ratio?

e. list the final state of the cache, with each valid entry represented as a record of

2. For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. TagIndex Offset 31-109-540 Starting from power on, the following byte-addressed cache references are recorded. Address 0 4 16 132 232 160 1024 4 140 3100 180 2180