An architecture has two separate caches, Data cache with $15\%$ miss

rate and $80$ cycle penalty, and Instruction cache with $10\%$ miss rate

and $80$ cycle penalty. IT also has a TLB with $9\%$ miss rate and $50$ cycle

penalty. Break down of instructions is $50\%$ ALU, $15\%$ Branch and $35\%$

Load$/$Store with CPIs $4,2$ and $5$ respectively. What is the real CPI?

What is the speedup thanks to the TLB$?$ What is the speedup thanks

to the two caches and TLB$?$An architecture has two separate caches, Data cache with $15\%$ miss

rate and $80$ cycle penalty, and Instruction cache with $10\%$ miss rate

and $80$ cycle penalty. IT also has a TLB with $9\%$ miss rate and $50$ cycle

penalty. Break down of instructions is $50\%$ ALU, $15\%$ Branch and $35\%$

Load$/$Store with CPIs $4,2$ and $5$ respectively. What is the real CPI?

What is the speedup thanks to the TLB$?$ What is the speedup thanks

to the two caches and TLB$?$