Assume that the logic blocks needed to implement a processor's datapath have the following latencies: a, if the only thing we need to do in a processor is fetch consecutive instructions (Figure 4.6), what would the cycle time be? b, Consider a datapath similar to the one in Figure 4.11, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would be the cycle time for this datapath? c, Repeat part b), but this time we need to support only conditional PC-Relative branches. d, Which kind of instructions require datapath element Shift-Left-2? e, Assume that we only support beq and add instructions, discuss how changes in the given latency of shift-Left-2 affect the cycle time of the processor. Assume that the latencies of other resources do not change. Assume that the logic blocks needed to implement a processor's datapath have the following latencies: a, if the only thing we need to do in a processor is fetch consecutive instructions (Figure 4.6), what would the cycle time be? b, Consider a datapath similar to the one in Figure 4.11, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would be the cycle time for this datapath? c, Repeat part b), but this time we need to support only conditional PC-Relative branches. d, Which kind of instructions require datapath element Shift-Left-2? e, Assume that we only support beq and add instructions, discuss how changes in the given latency of shift-Left-2 affect the cycle time of the processor. Assume that the latencies of other resources do not change