D- Q3. 4.4 Problems in this exercise assume that logic blocks needed to implement a processor's data path have the following latencies: I-Mem Add Mux ALU Regs Mem Sign-Extend Shift-Left-2 200ps 7Ops 20ps 90ps 90ps 250ps 15ps 1 Ops 4.4.1 [10] If the only thing we need to do in a processor is fetch consecutive instructions (Figure 4.6), what would the cycle time be? 4.4.2 [10] Consider a data path similar to the one in Figure 4.11, but for a processor that only has one type of instruction: unconditional PC-relative branch. What would the cycle time be for this data path? 4.4.3 [10] Repeat 4.4.2, but this time we need to support only conditional PC-relative branches The remaining three problems in this exercise refer to the data path element Shift left-2: 4.4.4 [10] Which kinds of instructions require this resource? 4.4.3 [20] For which kinds of instructions (if any) is this resource on the critical path? 4.4.6 [10] Assuming that we only support heq and add instructions, discuss how changes in the given latency of this resource affect the cycle time of the processer. Assume that the latencies of other resources do not change