Question: b ) Create a module in Verilog that implements the state machine. The module should have the following signals: Inputs A , CLK , and

b) Create a module in Verilog that implements the state machine. The module
should have the following signals: Inputs A, CLK, and RST. Outputs F and G.
c) Create a test bench module that demonstrates your FSM. You should see the
outputs at FG=00, FG=01, and FG=11 each at least once.
Hint: Use if/else statements or a case statement to reduce your implementation
time.

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