Below is a list of block sequences requested by the CPU. 1.3.9.3.1 For each of these requests, given a direct-mapped cache with 4 blocks 2-way set associative cache, fully associative cache (6-way set associative cache). State whether each memory address reference is a hit or a miss, assuming the cache is initially empty. Replacement Rule: LRU. Address Direct-mapped Cache: HitMiss 2 way associative cache Fully associative cache: Hit/Miss Hit/Miss 1 3 > Remaining Time: 46 minutes, 54 seconds Question completion Status 3 9 1 %. Miss rate for Direct-mapped cache = v % Miss rate for 2-associative cache = %. Miss rate for Fully associative cache =- Which cache is the best in terms of hit rate