Cache block size $($B$)$ can affect both miss rate and miss penalty. Assuming a machine with

a cache access time of $1$ clock cycle, find the block size that minimizes the AMAT given the

following misses per instruction for various block sizes.

$($a$)$ What is the optimal block size for a miss penalty of $10\backslash$times B clock cycles?

$($b$)$ What is the optimal block size for a miss penalty of $32+$B clock cycles?

$($c$)$ For a constant miss penalty, what is the optimal block size?