Question: Can someone help me with the test bench for this dflipflop module dff (Q, Data, Clk, Reset, enable); input Data, Clk, Reset, enable; output reg

Can someone help me with the test bench for this dflipflop

module dff (Q, Data, Clk, Reset, enable);

input Data, Clk, Reset, enable;

output reg Q;

always @ ( posedge Clk or negedge Reset)

if (~Reset) begin

Q <= 1'b0;

end

else if (enable) begin

Q <= Data;

end

endmodule

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