Question: module Main ( out _ 0 , CLK , inp _ 0 , reset, present _ 0 2 3 ) ; output [ 1 5

module Main(out_0, CLK, inp_0, reset, present_023);
output [15:0] out_0;
input inp_0, reset, present_023, CLK;
wire and_0_out, \0_Q ,\1_Q ,\2_Q ,\3_Q ,\4_Q ,\5_Q ,\6_Q ,\7_Q ,\8_Q ,\9_Q ,\10_Q , xor_2_out, \11_Q ,\12_Q , xor_1_out, \13_Q , xor_0_out, \14_Q ,\15_Q ;
wire [15:0] Splitter_0_cmb;
assign and_0_out = inp_0 & CLK;
DflipFlop \0(\0_Q ,, and_0_out, xor_2_out, reset | present_023,,);
assign Splitter_0_cmb ={\15_Q ,\14_Q ,\12_Q ,\13_Q ,\11_Q ,\10_Q ,\9_Q ,\8_Q ,\7_Q ,\6_Q ,\5_Q ,\4_Q ,\3_Q ,\2_Q ,\1_Q ,\0_Q };
assign out_0= Splitter_0_cmb;
DflipFlop \1(\1_Q ,, and_0_out, \0_Q , reset | present_023,,);
DflipFlop \2(\2_Q ,, and_0_out, \1_Q , reset | present_023,,);
DflipFlop \3(\3_Q ,, and_0_out, \2_Q , reset | present_023,,);
DflipFlop \4(\4_Q ,, and_0_out, \3_Q , reset | present_023,,);
DflipFlop \5(\5_Q ,, and_0_out, \4_Q , reset | present_023,,);
DflipFlop \6(\6_Q ,, and_0_out, \5_Q , reset | present_023,,);
DflipFlop \7(\7_Q ,, and_0_out, \6_Q , reset | present_023,,);
DflipFlop \8(\8_Q ,, and_0_out, \7_Q , reset | present_023,,);
DflipFlop \9(\9_Q ,, and_0_out, \8_Q , reset | present_023,,);
DflipFlop \10(\10_Q ,, and_0_out, \9_Q , reset | present_023,,);
assign xor_2_out =\10_Q ^ xor_1_out;
DflipFlop \11(\11_Q ,, and_0_out, \10_Q , reset | present_023,,);
DflipFlop \12(\12_Q ,, and_0_out, \11_Q , reset | present_023,,);
assign xor_1_out =\12_Q ^ xor_0_out;
DflipFlop \13(\13_Q ,, and_0_out, \12_Q , reset | present_023,,);
assign xor_0_out =\13_Q ^\15_Q ;
DflipFlop \14(\14_Q ,, and_0_out, \13_Q , reset | present_023,,);
DflipFlop \15(\15_Q ,, and_0_out, \14_Q , reset | present_023,,);
endmodule
module DflipFlop(q, q_inv, clk, d, a_rst, pre, en);
parameter WIDTH =1;
output reg [WIDTH-1:0] q, q_inv;
input clk, a_rst, pre, en;
input [WIDTH-1:0] d;
always @ (posedge clk or posedge a_rst)
if (a_rst) begin
q <='b0;
q_inv <='b1;
end else if (en ==0) ;
else begin
q <= d;
q_inv <= ~d;
end
endmodule
`timescale 1ns/1ps
module TestBench();
reg inp_0, reset, present_023, CLK;
wire [15:0] out_0;
Main DUT0(out_0, CLK, inp_0, reset, present_023);
always begin
#10 CLK = ~CLK; // Toggle clock every 10 time units
end
initial begin
CLK =0;
inp_0=0;
reset =1; // Assert reset initially
present_023=0;
#20 reset =0; // Deassert reset after 20 time units
#20 present_023=1; // Assert present_023 for 20 time units
#20 present_023=0; // Deassert present_023
// Apply input data
#20 inp_0=1; // Set inp_0 to 1 to provide input data
#40 inp_0=0;
#20 inp_0=1;
#40 inp_0=0;
#200 $finish; // Terminate simulation after 200 time units
end
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, TestBench);
end
always @(posedge CLK) begin
$display("out_0=%b (%h)", out_0, out_0);
end
endmodule
Separate out the design file and the testbench file so you can simulate the circuit using
the EDA playground.
c. You will need to edit the testbench and write code to toggle the reset and preset and
enable the clock.
d. You will need to edit the design file so that the DD flipflop works the same as it does in
CircuitVerse (code to use the preset_023 signal must be integrated into the reset if
statement).
e. Run a simulation to generate 10 numbers
f. Hand in your list of numbers in both binary and hexadecimal format.
g. Hand in a timing diagram of your simulation

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