Can someone help write this vhdl program? You should try to use only the synthesizable features of VHDL. In particular, only one "wait" statement is allowed in a process. The "wait for" statements are not allowed in your implementation, but might be used in your test benches.

Develop a behavioral VHDL model for a 4-to-l word multiplexer (MUX). Your model should work with arbitrary length words: i.e.. you should not place hard constraints on the lengths of inputs and outputs. Develop a test bench for your MUX that demonstrates each function for all possible permutations of inputs other than the 4 words