can you explain the Verilog code line by line, please

module convertor(num, frac, total); input [15:0] num; input [15:0] frac; wire Sig; wire [7:0] Exp; wire [22:0] Mant; output [31:0] total;

reg [7:0] n; wire [31:0] ment;

wire [15:0] numReg; wire [15:0] fracReg;

//assign {numReg,fracReg} = num[15] ? {num,frac}^32'h7FFFFFFF+1'b1 : {num,frac};

assign numReg = num; assign fracReg = frac;

always@(*) casex({numReg[14:0],fracReg}) 31'b1xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx: n=14; 31'b01x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx: n=13; 31'b001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx: n=12; 31'b000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx: n=11; 31'b000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx: n=10; 31'b000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx: n=9; 31'b000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx: n=8; 31'b000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx: n=7; 31'b000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx: n=6; 31'b000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx: n=5; 31'b000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx: n=4; 31'b000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx: n=3; 31'b000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx: n=2; 31'b000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx: n=1; 31'b000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx: n=0; 31'b000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx: n=-1; 31'b000_0000_0000_0000_01xx_xxxx_xxxx_xxxx: n=-2; 31'b000_0000_0000_0000_001x_xxxx_xxxx_xxxx: n=-3; 31'b000_0000_0000_0000_0001_xxxx_xxxx_xxxx: n=-4; 31'b000_0000_0000_0000_0000_1xxx_xxxx_xxxx: n=-5; 31'b000_0000_0000_0000_0000_01xx_xxxx_xxxx: n=-6; 31'b000_0000_0000_0000_0000_001x_xxxx_xxxx: n=-7; 31'b000_0000_0000_0000_0000_0001_xxxx_xxxx: n=-8; 31'b000_0000_0000_0000_0000_0000_1xxx_xxxx: n=-9; 31'b000_0000_0000_0000_0000_0000_01xx_xxxx: n=-10; 31'b000_0000_0000_0000_0000_0000_001x_xxxx: n=-11; 31'b000_0000_0000_0000_0000_0000_0001_xxxx: n=-12; 31'b000_0000_0000_0000_0000_0000_0000_1xxx: n=-13; 31'b000_0000_0000_0000_0000_0000_0000_01xx: n=-14; 31'b000_0000_0000_0000_0000_0000_0000_001x: n=-15; 31'b000_0000_0000_0000_0000_0000_0000_0001: n=-16; default: n=0; endcase

assign Exp = 127+n;

assign ment = {numReg,fracReg}<<(16-n); assign Mant = ment[31:9];

assign Sig = num[15]; assign total = {Sig,Exp,Mant}; endmodule