Consider a $32-$bit byte address, a direct$-$mapped cache of size $64$K bytes with

each block of size four words. A series of memory accesses occur as follows

$($assume all states are reset initially$)$: $0$xDF$105670,0$xDF$10567$C$,$

$0$x$23$A$033$A$0,0$x$23$A$034$A$0,0$xDF$105678.$ The hit access is

$($a$)0$xDF$10567$C$.$

$($b$)0$X$23$A$034$A$0.$

$($c$)0$XDF$105678.$

$($d$)0$x$23$A$033$A$0.$