Consider a multi-cycle floating-point pipelined processor with the four execution units shown below. Depending on the execution unit used, the EXE stage has the following latency: Integer unit: 1 clock cycle FP-adder (pipelined): 4 clock cycles Multiplier (pipelined): 7 clock cycles Divider (unpipelined): 25 clock cycles Assume that Integer registers are called Rx (R0, R1, ...) and FP registers are called Fy (F0, F1, F2).

a) Provide a sequence of instructions incurring a STRUCTURAL HAZARD

b)Provide a sequence of instructions incurring a RAW HAZARD

c)Provide a sequence of instructions incurring a WAW HAZARD

d)Provide a sequence of instructions incurring a WAR HAZARD