Consider the following pipelined processor we studied in class $($registers are written in the first half of the cycle and read in the second half of the cycle and that branches are resolved during execute$).$ Assume that initial values of all registers are Zero and memory are $50.$

In this part

i$)$ Assume there is forwarding hardware. $($Data forwarding is Active means instruction won't have to wait in the decode stage for read after write $($if there is any data dependency$))$

ii$)$ Assumes all the branch instruction is NOT going to be taken. $($Means if the prediction was wrong then you will have to flush the entire circuit and fetch new instruction accordingly$)$

Fill in the pipeline timing diagram at the bottom showing the execution of the DLX code given below. Use the following codes: $F=$ fetch, $D=$ decode, $E=$ execute, $M=$ memory access, $W=$ write back, $s=$ stall. The first instruction is filled in for you. Show all the executed instructions. $[$List the instruction number corresponding to your pipeline diagram in the leftmost column. The numbers above each column are provided to help you count cycles.$]$

Fill in write back cycle of each instruction:

$\backslash$table$[[$Instr$.$ No$.,,$Instruction,Write back cycle$],[(1),$addi,rl$,$r$0,5,4],[(2),$Sw$,$r$1,4($r$0),],[(3),$LW$,$r$3,4($r$0),],[(4),$beq,r$1,$r$3,$L$1,],[(5),$sub,r$7,$r$2,$r$3,],[(6),$or$,$r$6,$r$2,$r$0,],[(7),$L$1$:$,$r$5,4($r$0),],[(8),$beq,r$5,$r$4,$L$2,],[(9),$sub,r$7,$r$3,$r$8,],[(10),$add,r$1,$r$2,$r$7,],[(11),$xor,r$4,$r$3,$r$6,],[(12),$SW$,$r$1,12($r$2),],[(13),$Sw$,$r$4,20($r$1),],[(14),$add,r$1,$r$4,$r$5,]]$

This is the same as question I but now

i$)$ Assumes there is NO FORWARDING hardware. $($Mcans instructions will have to wait in the decode stage for read after write $($if there is any data dependency$))$

ii$)$ Assumes all the branch instruction is going to be taken. $($Means if the prediction was wrong then you will have to flush the entire circuit and fetch new instruction accordingly$)$

Fill in writc back cyclc of cach instruction:

$\backslash$table$[[$instruction$,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19],[(1),$F$,$D$,$E$,$M$,$W$,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,,,,,,]]$