Exercise 2 Following is a simple pipeline; with a bypass from the output of the MEM stage to the EX stage. Assume that the register file is written in the first half and read in the second half of the clock cycle. Hence, a register value can be written and read in the same cycle. IF ID EX MEM WB Data Mem Reg. File Inst Reg. Fik LU insert Os Harard ' Stall (a)What's the purpose of bypassing? Is it always possible to use? why or why not (b) Give an example to show how the bypassing in the previous chart can get better performance (reduce the execution time). You need show a sequence of instructions and detailed 5-stage execution of each instruction without and then with the bypassing