Consider two different implementations of the same instruction set architecture $($ISA$).$ The

instructions can be divided into four classes according to their CPI $($class A$,$ B$,$ C$,$ and D$).$ P$1$

with a clock rate of $2\mathrm{.}5$ GHz have CPIs of $1,2,3,$ and $3$ for each class, respectively. P$2$ with a

clock rate of $3$ GHz and CPIs of $2,2,2,$ and $2$ for each class, respectively.