Question: Design a vhdl code a timer capable of running from 0min:00sec to 9min:59sec (figure 2). The circuit must have start, stop, and reset buttons. The

Design a vhdl code a timer capable of running from 0min:00sec

Design a vhdl code a timer capable of running from 0min:00sec to 9min:59sec (figure 2). The circuit must have start, stop, and reset buttons. The outputs must be SSD coded. Consider that a reliable 1 Hz clock signal is available

min sec sec start | stop-> reset 8.89 M min sec sec start | stop-> reset 8.89 M

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