Design an $8-$bit register with $3$ control inputs $s1,s0,$ and load, $8$ data inputs I$7...$I$0,$ and $8$

data outputs $Q7$dotsQ$0.$ s$1$s $0=00$ means maintain the present value, $s1s0=01$ means negate th

contents, $s1s0=10$ shifts the content right by $2$ bits each clock cycle and fill the vacated bits

with the original right$-$most bit, $s1s0=11$ is to swap the high nibble $($a nibble is $4$ bits$)$ with

the low nibble, so $11110000$ would become $00001111,$ and $11000101$ would become

When load $=1,8$ data inputs I$7...$I$0$ are loaded to the register. Draw schematic

using building blocks. $(25$ Points$)$

note that an additional signal load is added. When load$=1,8$ data inputs I$7...$I$0$ are loaded to the register.

Attention that any bus with customized order is not allowed. You can only use bus to merge your signals. Additionally, you should label the highest digit of you merged signal when using the bus to eliminate the ambiguity.