Don't forget the clock (clk) and Reset inputs. Then draw your next state logic and output logic. Remember to draw clear schematics. Messy or unclear schematics will receive no credit. 1. [50 pts total] Finite state machine (FSM) design: Design an FSM that implements a modulo 8 counter, also known as a 3-bit counter. The FSM should output the following sequence: 000-001-010-011-100-101-110-111 and then repeat indefinitely. Upon reset, the FSM should start outputting 000 and so on. Be sure to show all design steps (i.e., state transition diagram, state transition table, output table, state encodings, next state and output equations, and circuit schematic)