$!!!!$ Don't use assign, rather use buf $!!!!$

Objective:

To implement a Verilog gate level model for $32-$bit Signed multiplier.

Outcome:

Gate level implementation for the following components.

MULT$32\_$U

MULT$32$

MUX$32\_2$x$1$

Instruction:

Continue with your Modelsim Project$03$ as in Lab Assignment $03$

Complete gate level description of following components in mux.v file.

MUX$1\_2\backslash$times $1$

MUX$32\_2$x$1$

Complete gate level description of following components in mult.v file

MULT$32\_$U

MULT$32$

Compile entire Project$03$ and simulate following modules in ModelSim simulator.

MUX$32\_2$x$1\_$TB

MULT$\_$U$\_$TB

MULT$\_$TB

Observe corresponding outcomes on waveform windows and fix any issue.

Each testbench will generate corresponding output file.

OUTPUT$/$mux$32\_2$x$1\_$tb$.$out

OUTPUT$/$mult$32\_$u$\_$tb$.$out

OUTPUT$/$mult$32\_$tb$.$out

This should match with corresponding golden output file in CS$147-$Project$03/$GOLDEN$/$ directory.

mux$32\_2$x$1\_$tb$.$out.golden

mult$32\_$u$\_$tb$.$out.golden

mult$32\_$tb$.$out.golden

Add more testing in these testbenches to make sure outcome is correct.