Employ structural VHDL in your design by implementing the circuit shown in Figure using port map statements to implement the AND and OR gates. Use concurrent signal assignment statements to obtain the required negated values of the input signals. Write entity-architecture descriptions for the AND and OR gate components using concurrent VHDL (i.e. the and oper- ator for the AND gate). You may use a concurrent signal assignment statement in your top-level code to negate the output which drives the LED output

library IEEE; use IEEE.std_logic_1164.all; 

entity sum_of_minterms is port( a,b,c : in std_logic; 

 output : out std_logic); end sum_of_minterms; 

The function may be expressed in sum-of-minterms form as: OUT = A B C + A B C + A B C The gate level hardware implementation of the function is shown in Figure 1 on is shown in Figure1 OUT