entity imm_Gen is

Port (

InstCode : in std_logic_vector (31 downto 0);

ImmOut : out std_logic_vector (31 downto 0));

end imm_Gen;

architecture Behavioral of imm_Gen is

Another module that we need to add some lines to it is the Immediate Generator. For R-Type instructions when the Opcode is 0110011 there is no immediate value so the Imm Gen output is zero. For I-Type the Opcode is 0010011 or 0000011. For LW, ADDI, SLTI, NORI, ORI, and ANDI we extended the sign bit of the immediate value which is Instruction (31 downto 20). SLLI, SRLI, And SRAI are also I-Type with the same Opcode but the immediate value for these instructions is Instruction (24 downto 20). To nd the 32-bit output ll the upper positions with zero. For S-Type instruction with Opcode 0100011 the immediate value is split into two parts. One part is Instruction (11 downto 7) and the other one is Instruction (31 downto 25). First, we need to concatenate these two parts then sign extend the result. For Branch-Type instruction the Opcode is 1100011. Same as S-Type here the immediate value is split into two parts. One part is Instruction (11 downto 7) and the other one is Instruction (31 downto 25). Concatenate these two parts and sign extend the result.

Please use VHDL ONLY for this module and please do not change or add to the ENTITY.

Thank You