Question: I have the Project procedural as this: module Project 2 _ procedural ( input A , input B , input C , output F )

I have the Project procedural as this:
module Project2_procedural(
input A,
input B,
input C,
output F
);
reg F;
always @ (A, B, C)
if (A==0 & B==0 & (C==0| C==1))
begin
F =1'b1;
end
else if (A==0 & B==1 & C==0)
begin
F =1'b1;
end
else if (A==0 & B==1 & C==1)
begin
F =1'b0;
end
else if (A==1 & B==0 & C==0)
begin
F =1'b0;
end
else if (A==1 & B==0 & C==1)
begin
F =1'b0;
end
else if (A==1 & B==1 & C==0)
begin
F =1'b1;
end
else if (A==1 & B==1 & C==1)
begin
F =1'b0;
end
endmodule
I have the structural is this:
module project2_Structural(
input A,
input B,
input C,
output F
);
not (B_not, B);
or ( Z1, A, B);
or ( Z2, B_not, C);
nand (F, Z1, Z2);
endmodule
I have the continous as this:
module project2_continous(
input A,
input B,
input C,
output F
);
assign F = ~((A|B)&(~B|C));
endmodule
And I have the constraint as this:
set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33}[get_ports { A }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33}[get_ports { B }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33}[get_ports { C }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33}[get_ports { F }]; #IO_L18P_T2_A24_15 Sch=led[0]
What is wrong with the code and how do I get it to work? I tried to the bitstream to work with this and it's simply not working.
[Common 17-55] 'set_property' expects at least one object. ["C:/Users/KFC/Desktop/Lol/project_2/project_2.srcs/constrs_1/new/Proj2_Constraint.xdc":30]
[Vivado 12-584] No ports matched 'F'.["C:/Users/KFC/Desktop/Lol/project_2/project_2.srcs/constrs_1/new/Proj2_Constraint.xdc":30]
[Synth 8-6155] done synthesizing module 'Project2_Part2_Structural' (0#1)["C:/Users/KFC/Desktop/Lol/project_2/project_2.srcs/sources_1/new/Project2_Part2_Structural.v":7]
[Synth 8-6157] synthesizing module 'Project2_Part2_Structural' ["C:/Users/KFC/Desktop/Lol/project_2/project_2.srcs/sources_1/new/Project2_Part2_Structural.v":7]
[Synth 8-11241] undeclared symbol 'A_not', assumed default net type 'wire' ["C:/Users/KFC/Desktop/Lol/project_2/project_2.srcs/sources_1/new/Project2_Part2_Structural.v":16]
I have the Project procedural as this: module

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