Identify the error in the below system verilog code and Rectify

Code $01$:

module assingment$\_11$;

int count;

initial begin

forever begin

$display$("$Value of count $=\%0$d$",$ count$)$;

count$++$;

if$($count $==10)$;

break;

end

end

endmodule

Code $02$:

module assingment$\_11\_$code$02$ ;

int count;

begin

$display$("$Value of count $=\%0$d$",$ count$)$;

count$++$;

#$5$;

end

initial begin

#$30$;

$finish;

end

endmodule