Question: module my counter(clk, reset, counter); module mycounter_testbench(); reg clk, reset; wire (1:0) counter; input clk, reset; output (1:0) counter; reg (1:0) counter_up = 2'b00; my

module my counter(clk, reset, counter); module mycounter_testbench(); reg clk, reset; wire

(1:0) counter; input clk, reset; output (1:0) counter; reg (1:0) counter_up =

module my counter(clk, reset, counter); module mycounter_testbench(); reg clk, reset; wire (1:0) counter; input clk, reset; output (1:0) counter; reg (1:0) counter_up = 2'b00; my counter test(clk, reset, counter); always @(posedge clk, negedge reset) begin initial begin clk=0; forever #2 clk=clk; end initial begin reset=0; if(!reset) counter_up

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