Question: Multi - Cycle Arch. Given the following code. Assume that x and y are arrays of words and the base address of x is stored
MultiCycle Arch. Given the following code. Assume that x and y are arrays of words and the base address of x is stored in R and the base address of y is stored in R Assume that each add operation takes cycles to execute, each lw operation cycles, each store sw takes cycles, and each branch bne instruction takes cycles to execute. The T represents Temp registers. All numbers are in decimal.
add T zero, zero # T i
add T R zero # T address of xi
add T R zero # T address of yi
add T zero,
Loop: lw TT # Load T with MT value
add T T C # C is a constant value
sw TT # Store T to MT
add T T
add T T
add T T
: bne T T # Loops if branch is taken
: add T T
What is the PC value for the SW instruction?
Multiple choice Question
Calculate the branch target address?
Multiple choice Question
What happens after T becomes equal to T
Multiple choice Question
T increases by
Branch is taken
T is loaded with new value from memory
T increases by
What is the total number of instructions that get fully executed?
Multiple choice Question
How many cycles it take to execute all instructions in the given code?
Multiple choice Question
What is the final value of T
Multiple choice Question
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