Question: Multi-Cycle Arch . Given the following code. Assume that x and y are arrays of words and the base address of x is stored in
Multi-Cycle Arch. Given the following code. Assume that x and y are arrays of words and the base address of x is stored in R1 and the base address of y is stored in R2. Assume that each add operation takes 4 cycles to execute, each lw operation 5 cycles, each store sw takes 4 cycles, and each branch (bne) instruction takes 3 cycles to execute. The T represents Temp registers. All numbers are in decimal.
add T0, zero, zero # T0 = i = 0+0 = 0
add T1, R1, zero # T1 = address of x[i] + 0
add T2, R2, zero # T2 = address of y[i] + 0
add T3, zero, 201
Loop: lw T4, 0(T2) # Load T4 with M[T2+0] value
add T5, T4, C # C is a constant value
sw T5, 0(T1) # Store T5 to M[T1+0]
add T0, T0, 1
add T1, T1, 4
add T2, T2, 4
140: bne T0, T3, -7 # Loops if branch is taken
144: add T0, T0, 200
What is the PC value for the SW instruction?
200
135
124
120
Calculate the branch target address?
120
133
116
-7
What happens after T0 becomes equal to T3?
T0 increases by 200
T0 has the value of T0+(-7)
Branch is taken
T4 is loaded with new value from memory
What is the total number of instructions that get fully executed?
12
1412
144
201
How many cycles it take to execute all instructions in the given code?
48
804
576
5628
What is the final value of T0?
394
200
401
400
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