Multi$-$Cycle Arch. Given the following code. Assume that x and y are arrays of words and the base address of x is stored in R$1$ and the base address of y is stored in R$2.$ Assume that each add operation takes $3$ cycles to execute, each lw operation $4$ cycles, each store sw takes $3$ cycles, and each branch $($bne$)$ instruction takes $2$ cycles to execute. The"T$\text{'}$ represents Temp registers. All numbers are in decimal.Loop:$142$:$144$:add TO$,$ zero, zero add T$1,$ R$1,$ zero add T$2,$ R$2,$ zero add T$3,$ zero, $101$lw T$4,0($T$2)$ add T$5,$ T$4,$ C sw T$5,0($T$1)$ add TO$,$ TO$,1$add T$1,$ T$1,4$add T$2,$ T$2,4$bne TO$,$ T$3,-7$add TO$,$ TO$,100$# TO $=$ i $=0+0=0$# T$1=$ address of x$[$i $+0$# T$2=$ address of yi $+0$# Load T$4$ with M$[$T$2+0]$ value# C is a constant value# Store T$5$ to M$[$T$1+0]$# Loops if branch is takenWhat is the PC value for the SW instruction?$120128$