Multi-Cycle Arch. Given the following code. Assume that x and y are arrays of words and the base address of x is stored in R1 and the base address of y is stored in R2. Assume that each add operation takes 4 cycles to execute, each lw operation 5 cycles, each store sw takes 4 cycles, and each branch (bne) instruction takes 3 cycles to execute. The "T" represents Temp registers. All numbers are in decimal. add To, zero, zero # TO = i = 0+0 = 0 add T1, R1, zero # T1 = address of x[i] + 0 add T2, R2, zero # T2 = address of y[i] + 0 add T3, zero, 201 Loop: lw T4, 0(T2) # Load T4 with M[T2+0] value add T5, T4, #Cis a constant value sw T5, O(T1) #Store T5 to M[T1+0] add TO, TO, 1 add T1, T1,4 add T2, T2,4 140: bne TO, T3, -7 #Loops if branch is taken 144: add TO, TO, 200 What is the PC value for the SW instruction? O 120 O 135 O 124 O 200 Calculate the branch target address? 133 What happens after to becomes equal to 13? O T4 is loaded with new value from memory O Branch is taken OTO has the value of TO+(-7) OTO increases by 200 What is the total number of instructions that get fully executed? O 144 O 1412 0 201 O 12 How many cycles it take to execute all instructions in the given code? 804 O 5628 O 576 O 48 What is the final value of TO? O 401 O 394 O 400 O 200